$70.00

Xilinx Platform Cable USB ALTERA USB Blaster 2 in 1
[Xilinx Platform Cable USB ALTERA USB Blaster 2 in 1]

Xilinx Platform Cable USB ALTERA USB Blaster 2 in 1
Xilinx Platform Cable USB ALTERA USB Blaster 2 in 1
This product uses the officially consistent CY7C68013A+XC2C256 case. and only this compatibility case supports firmware upgrade!
The so-called upgrade is that IMPACT software refreshes the logical configuration of this XC2C256 through CY7C68013 to set the JTAG timing according to different devices and reserve new functions for future software versions. The XC2C256 is not used because it does not support runtime reconfiguration, giving up the possibility of compatibility and stability and supporting future versions.
The XC2C256 used in the downloader is XILINX's new COOL RUNNER series CPLD, which is the most expensive component of the whole downloader. The configuration interface of this CPLD is the IO connecting 68013. 68013 carries out new logical construction of this CPLD according to different settings and chip types, which is a visual judgment to determine whether it supports upgrading.
The verf level range is 1.2~5.5V. As official, 7 SN74LV2G125 chips are used as interface buffer isolation chips, and SRV05-4 array protection tubes are used for external IO protection.
1. Fully compatible with USB BLASTER and XILINX PLATFORM without any additional driver. Connect to the USB port, and it will be recognized as the downloader and automatically load the official driver.
2. The MCU and CPLD firmware of XILINX can be upgraded under official tools to keep the latest version of software.
3. There are two modes: ALTERA and XILINX. The mode switch toggle switch can automatically enumerate USB devices and automatically load drivers without plugging or unplugging USB cables.
4. Fully compatible with official USB in ALTERA mode_ BLASTER and NIOS debugging cannot work normally under various modes such as WORNING, JTAG, AS, and PS, and there is no common data verification error in AS mode (timing design is in place to meet the establishment and retention time of JTAG signals), nor is there any WARNING for NIOS debugging (because the original version query instructions are fully supported).
5. The power supply of the target board and the emulator is relatively independent and adaptive to the power supply of the target board, and there is a unique protection scheme to protect the CPLD inside the target board and the emulator to the greatest extent.
B) Speed:
XILINX is the same as the original one;
The ALTERA speed is configured in the JTAG mode of FPGA, which is equal to the original scheme. The download speed in the AS mode and the speed of writing CPLD are much faster than the original USB BLASTER. Especially when the configuration chip is burned, the speed is obviously superior to the original USB BLASTER. Therefore, it is strongly recommended to use the mass production line to save time and improve efficiency
XILINX is the same as the original one;
The ALTERA speed is configured in the JTAG mode of FPGA, which is equal to the original scheme. The download speed in the AS mode and the speed of writing CPLD are much faster than the original USB BLASTER. Especially when the configuration chip is burned, the speed is obviously superior to the original USB BLASTER. Therefore, it is strongly recommended to use the mass production line to save time and improve efficiency


The ALTERA USB BLASTER mode part of this downloader uses MAXII series CPLD acceleration. The following is the state transition diagram of the internal acceleration state machine:
This acceleration design is a "secret weapon" to improve the communication speed in JTAG mode and AS mode.



The following is a screen shot of the successful burning of SPI memory in xilinx mode under IMPACT tool.

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